Hossein Asadi, Dr.

Hossein Asadi

Visiting professor in the Efficient Computing and Storage Group

Johannes Gutenberg-Universität Mainz
Anselm-Franz-von-Bentzel-Weg 12
55128 Mainz, Germany

Phone: +49 6131 3937698
Fax: +49 6131 3926407
Email: hasadi@uni-mainz.de

 

 

 

About

Dr. Hossein Asadi is a visiting professor at the Computer Science Department of JGU since July 2021. He received the BSc and MSc degrees in computer engineering from Sharif University of Technology (SUT), Tehran, Iran, in 2000 and 2002, respectively, and the PhD degree in computer engineering from Northeastern University, Boston, MA, USA, in 2007. Prior visiting JGU, he has been a full professor in Department of Computer engineering at SUT. He has been the director of Sharif High-Performance Computing Center from 2015 to 2021. In the past few years, he received several prestigious awards from SUT including "Distinguished Researcher Award" in 2016, "Distinguished Research Institute Award" in 2016, "Distinguished Technology Award" in 2017, and "Distinguished Research Lab Award" in 2019. From 2006 to 2009, Dr. Asadi worked at EMC Corporation, headquartered in Hopkinton, MA, as a research scientist and senior hardware engineer. He was also a recipient of the Technical Award for the Best Robot Design from the International RoboCup Rescue Competition, organized by AAAI and RoboCup in 2001, a recipient of Best Paper Award at the 15th CSI International Symposium on Computer Architecture and Digital Systems (CADS) in 2010, and a recipient of Best Paper Award at IEEE/ACM Design, Automation, and Test in Europe (DATE) in 2019. His current research interests include data storage systems, solid-state drives, emerging non-volatile memories, operating systems, virtualization, cloud computing, and high-performance computing.

2021

  • Elham Cheshmikhani, Hamed Farbeh, and Hossein Asadi. 2021. 3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison. IEEE Transactions on Computers: 1–1. DOI
  • Mojtaba Tarihi, Soheil Azadvar, Arash Tavakkol, Hossein Asadi, and Hamid Sarbazi-Azad. 2021. Quick Generation of SSD Performance Models Using Machine Learning. IEEE Transactions on Emerging Topics in Computing: 1–1. DOI
  • Saba Ahmadian, Farhad Taheri, and Hossein Asadi. 2021. Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems. IEEE Transactions on Emerging Topics in Computing 9, 4: 1914–1929. DOI
  • Saba Ahmadian, Reza Salkhordeh, Onur Mutlu, and Hossein Asadi. 2021. ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 32, 10: 2415–2433. DOI Author/Publisher URL
  • Shahriar Ebrahimi, Reza Salkhordeh, Seyed Ali Osia, Ali Taheri, Hamid R Rabiee, and Hossein Asadi. 2021. RC-RNN: Reconfigurable Cache Architecture for Storage Systems Using Recurrent Neural Networks. IEEE Transactions on Emerging Topics in Computing: 1–1. DOI
  • Zeinab Seifoori, Hossein Asadi, and Mirjana Stojilovic. 2021. Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing. IEEE Access 9: 115599–115619. DOI

2020

  • Elham Cheshmikhani, Hamed Farbeh, and Hossein Asadi. 2020. A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches. IEEE TRANSACTIONS ON RELIABILITY 69, 2: 594–610. DOI Author/Publisher URL
  • Mostafa Hadizadeh, Elham Cheshmikhani, and Hossein Asadi. 2020. STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC Allocation. In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). DOI
  • Mostafa Kishani, Saba Ahmadian, and Hossein Asadi. 2020. A Modeling Framework for Reliability of Erasure Codes in SSD Arrays. IEEE TRANSACTIONS ON COMPUTERS 69, 5: 649–665. DOI Author/Publisher URL

2019

  • Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Joerg Henkel, and Hossein Asadi. 2019. Estimating and Mitigating Aging Effects in Routing Network of FPGAs. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 27, 3: 651–664. DOI Author/Publisher URL
  • Elham Cheshmikhani, Hamed Farbeh, Seyed Ghassem Miremadi, and Hossein Asadi. 2019. TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches. IEEE TRANSACTIONS ON COMPUTERS 68, 3: 455–470. DOI Author/Publisher URL
  • Mostafa Kishani, Mehdi Tahoori, and Hossein Asadi. 2019. Dependability Analysis of Data Storage Systems in Presence of Soft Errors. IEEE TRANSACTIONS ON RELIABILITY 68, 1: 201–215. DOI Author/Publisher URL
  • Omid Ranjbar, Siavash Bayat-Sarmadi, Fatemeh Pooyan, and Hossein Asadi. 2019. A Unified Approach to Detect and Distinguish Hardware Trojans and Faults in SRAM-based FPGAs. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 35, 2: 201–214. DOI Author/Publisher URL
  • Reza Salkhordeh, Mostafa Hadizadeh, and Hossein Asadi. 2019. An Efficient Hybrid I/O Caching Architecture Using Heterogeneous SSDs. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 30, 6: 1238–1250. DOI Author/Publisher URL
  • Reza Salkhordeh, Onur Mutlu, and Hossein Asadi. 2019. An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories. IEEE TRANSACTIONS ON COMPUTERS 68, 8: 1114–1130. DOI Author/Publisher URL
  • Sajjad Tamimi, Zahra Ebrahimi, Behnam Khaleghi, and Hossein Asadi. 2019. An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 38, 3: 466–479. DOI Author/Publisher URL
  • Zeinab Seifoori, Hossein Asadi, and Mirjana Stojilovic. 2019. A Machine Learning Approach for Power Gating the FPGA Routing Network. In 2019 International Conference on Field-Programmable Technology (ICFPT). DOI

2018

  • Behnam Khaleghi and Hossein Asadi. 2018. A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 65, 7: 2196–2209. DOI Author/Publisher URL
  • Mostafa Kishani and Hossein Asadi. 2018. Modeling Impact of Human Errors on the Data Unavailability and Data Loss of Storage Systems. IEEE TRANSACTIONS ON RELIABILITY 67, 3: 1111–1127. DOI Author/Publisher URL
  • Reza Salkhordeh, Shahriar Ebrahimi, and Hossein Asadi. 2018. ReCA: An Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 29, 7: 1605–1620. DOI Author/Publisher URL
  • Zeinab Seifoori, Zahra Ebrahimi, Behnam Khaleghi, and Hossein Asadi. 2018. Introduction to Emerging SRAM-Based FPGA Architectures in Dark Silicon Era. In DARK SILICON AND FUTURE ON-CHIP SYSTEMS. 259–294. DOI Author/Publisher URL

2017

  • Mostafa Kishani, Reza Eftekhari, and Hossein Asadi. 2017. Evaluating impact of human errors on the availability of data storage systems. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. DOI
  • Zahra Ebrahimi, Behnam Khaleghi, and Hossein Asadi. 2017. PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era. IEEE TRANSACTIONS ON COMPUTERS 66, 6: 982–995. DOI Author/Publisher URL
  • Zeinab Seifoori, Behnam Khaleghi, and Hossein Asadi. 2017. A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017. DOI

2016

  • Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jorg Henkel, and Hossein Asadi. 2016. Stress-aware routing to mitigate aging effects in SRAM-based FPGAs. In 2016 26th International Conference on Field Programmable Logic and Applications (FPL). DOI
  • Hamed Farbeh, Nooshin Sadat Mirzadeh, Nahid Farhady Ghalaty, Seyed-Ghassem Miremadi, Mahdi Fazeli, and Hossein Asadi. 2016. A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 24, 11: 3296–3309. DOI Author/Publisher URL
  • Hossein Asadi, Paolo Ienne, and Hamid Sarbazi-Azad. 2016. Guest Editors’ Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems. IEEE TRANSACTIONS ON COMPUTERS 65, 4: 1006–1009. DOI Author/Publisher URL
  • Hossein Asadi, Paolo Ienne, and Hamid Sarbazi-Azad. 2016. Introduction: Special Section on Architecture of Future Many Core Systems. MICROPROCESSORS AND MICROSYSTEMS 46: 219–220. DOI Author/Publisher URL
  • Mojtaba Ebrahimi, Hossein Asadi, Rajendra Bishnoi, and Mehdi B Tahoori. 2016. Layout-Based Modeling and Mitigation of Multiple Event Transients. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 35, 3: 367–379. DOI Author/Publisher URL
  • Mojtaba Tarihi, Hossein Asadi, Alireza Haghdoost, Mohammad Arjomand, and Hamid Sarbazi-Azad. 2016. A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization. IEEE TRANSACTIONS ON COMPUTERS 65, 6: 1678–1691. DOI Author/Publisher URL
  • Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, and Hossein Asadi. 2016. Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 24, 12: 3489–3498. DOI Author/Publisher URL

2015

  • Behnam Khaleghi, Ali Ahari, Hossein Asadi, and Siavash Bayat-Sarmadi. 2015. FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic. IEEE EMBEDDED SYSTEMS LETTERS 7, 2: 46–50. DOI Author/Publisher URL
  • Iman Ahmadpour, Behnam Khaleghi, and Hossein Asadi. 2015. An efficient reconfigurable architecture by characterizing most frequent logic functions. In 2015 25th International Conference on Field Programmable Logic and Applications (FPL). DOI
  • Mojtaba Tarihi, Hossein Asadi, and Hamid Sarbazi-Azad. 2015. DiskAccel. In Proceedings of the 2015 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems. DOI
  • Reza Salkhordeh, Hossein Asadi, and Shahriar Ebrahimi. 2015. Operating system level data tiering using online workload characterization. JOURNAL OF SUPERCOMPUTING 71, 4: 1534–1562. DOI Author/Publisher URL
  • Sadegh Yazdanshenas, Hossein Asadi, and Behnam Khaleghi. 2015. A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 23, 9: 1868–1878. DOI Author/Publisher URL
  • Saeideh Alinezhad Chamazcoti, Ziba Delavari, Seyed Ghassem Miremadi, and Hossein Asadi. 2015. On endurance and performance of erasure codes in SSD-based storage systems. MICROELECTRONICS RELIABILITY 55, 11: 2453–2467. DOI Author/Publisher URL

2014

  • 2014. Computer Networks and Distributed Systems. Springer International Publishing. DOI
  • 2014. Artificial Intelligence and Signal Processing. Springer International Publishing. DOI
  • Ali Ahari, Behnam Khaleghi, Zahra Ebrahimi, Hossein Asadi, and Mehdi B Tahoori. 2014. Towards dark silicon era in FPGAs using complementary hard logic design. In 2014 24th International Conference on Field Programmable Logic and Applications (FPL). DOI
  • Ali Ahari, Hossein Asadi, and Mehdi B Tahoori. 2014. Emerging Non-Volatile Memory technologies for future low power reconfigurable systems. In 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC). DOI
  • Ali Ahari, Hossein Asadi, Behnam Khaleghi, and Mehdi B Tahoori. 2014. A power-efficient reconfigurable architecture using PCM configuration technology. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014. DOI
  • Hossein Asadi, Alireza Haghdoost, Morteza Ramezani, Nima Elyasi, and Amirali Baniasadi. 2014. CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors. MICROELECTRONICS RELIABILITY 54, 5: 1009–1021. DOI Author/Publisher URL
  • Sadegh Yazdanshenas and Hossein Asadi. 2014. Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 61, 10: 798–802. DOI Author/Publisher URL
  • Siavash Rezaei, Seyed Ghassem Miremadi, Hossein Asadi, and Mandi Fazeli. 2014. Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates. MICROELECTRONICS RELIABILITY 54, 6-7: 1412–1420. DOI Author/Publisher URL

2013

  • Amir Mahdi Hosseini Monazzah, Hamed Farbeh, Seyed Ghassem Miremadi, Mahdi Fazeli, and Hossein Asadi. 2013. FTSPM: A Fault-Tolerant ScratchPad Memory. In 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN). DOI
  • F Rajaei Salmasi, H Asadi, and M GhasemiGol. 2013. Impact of stripe unit size on performance and endurance of SSD-based RAID arrays. SCIENTIA IRANICA 20, 6: 1978–1998. Author/Publisher URL
  • M Ebrahimi, Liang Chen, H Asadi, and M B Tahoori. 2013. CLASS: Combined logic and architectural soft error sensitivity analysis. In 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC). DOI
  • Mohammad Hossein Hajkazemi, Amirali Baniasadi, and Hossein Asadi. 2013. FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications. In 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors. DOI
  • Mojtaba Ebrahimi, Hossein Asadi, and Mehdi B Tahoori. 2013. A layout-based approach for multiple event transient analysis. In Proceedings of the 50th Annual Design Automation Conference on - DAC ’13. DOI
  • Mojtaba Ebrahimi, Seyed Ghassem Miremadi, Hossein Asadi, and Mahdi Fazeli. 2013. Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 21, 8: 1454–1468. DOI Author/Publisher URL
  • Saeideh Alinezhad Chamazcoti, Seyed Ghassem Miremadi, and Hossein Asadi. 2013. On endurance of erasure codes in SSD-based storage systems. In The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013). DOI
  • Zana Ghaderi, Seyed Ghassem Miremadi, Hossein Asadi, and Mahdi Fazeli. 2013. HAFTA: Highly Available Fault-Tolerant Architecture to Protect SRAM-Based Reconfigurable Devices Against Multiple Bit Upsets. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY 13, 1: 203–212. DOI Author/Publisher URL

2012

  • Hossein Asadi, Mehdi B Tahoori, Mahdi Fazeli, and Seyed Ghassern Miremadi. 2012. Efficient algorithms to accurately compute derating factors of digital circuits. MICROELECTRONICS RELIABILITY 52, 6: 1215–1226. DOI Author/Publisher URL

2010

  • Alireza Haghdoost, Hossein Asadi, and Amirali Baniasadi. 2010. Using Input-to-Output Masking for System-level Vulnerability estimation in high-performance processors. In 2010 15th CSI International Symposium on Computer Architecture and Digital Systems. DOI
  • Alireza Haghdoost, Hossein Asadi, and Amirali Baniasadi. 2010. System-Level Vulnerability Estimation for Data Caches. In 2010 IEEE 16th Pacific Rim International Symposium on Dependable Computing. DOI
  • Hossein Asadi and Mehdi B Tahoori. 2010. Soft error modeling and remediation techniques in ASIC designs. MICROELECTRONICS JOURNAL 41, 8: 506–522. DOI Author/Publisher URL
  • Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, and Mehdi Baradaran Tahoori. 2010. A Fast Analytical Approach to Multi-cycle Soft Error Rate Estimation of Sequential Circuits. In 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools. DOI
  • Mahdi Fazeli, Seyed Ghassem Miremadi, Hossein Asadi, and Seyed Nematollah Ahmadian. 2010. A fast and accurate multi-cycle soft error rate estimation approach to resilient embedded systems design. In 2010 IEEE/IFIP International Conference on Dependable Systems & Networks (DSN). DOI

2009

  • M B Tahoori, H Asadi, B Mullins, and D R Kaeli. 2009. Obtaining FPGA soft error rate in high performance information systems. MICROELECTRONICS RELIABILITY 49, 5: 551–557. DOI Author/Publisher URL

2007

  • Brian Mullins, Hossein Asadi, Mehdi B Tahoori, David Kaeli, Kevin Granlund, Rudy Bauer, and Scott Romano. 2007. Case Study: Soft Error Rate Analysis in Storage Systems. In 25th IEEE VLSI Test Symmposium (VTS’07). DOI
  • Hossein Asadi and Mehdi B Tahoori. 2007. Analytical techniques for soft error rate Modeling and mitigation of FPGA-based designs. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 15, 12: 1320–1331. DOI Author/Publisher URL
  • Hossein Asadi, Mehdi B Tahoori, and Chandra Tirumurti. 2007. Estimating Error Propagation Probabilities with Bounded Variances. In 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007). DOI
  • Hossein Asadi, Mehdi B Tahoori, Brian Mullins, David Kaeli, and Kevin Granlund. 2007. Soft error susceptibility analysis of SRAM-based FPGAs in high-performance information systems. IEEE TRANSACTIONS ON NUCLEAR SCIENCE 54, 6: 2714–2726. DOI Author/Publisher URL

2006

  • Hossein Asadi and Mehdi Tahoori. 2006. Soft Error Derating Computation in Sequential Circuits. In 2006 IEEE/ACM International Conference on Computer Aided Design. DOI
  • Vilas Sridharan, Hossein Asadi, Mehdi B Tahoori, and David Kaeli. 2006. Reducing data cache susceptibility to soft errors. IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING 3, 4: 353–364. DOI Author/Publisher URL

Not dated

  • Hossein Asadi, Reza Salkhordehhaghighi, and Shahriyar Ebrahimi. Reconfigurable caching. Author/Publisher URL